The present invention relates to an analog-to-digital converter comparator circuit and particularly to such a circuit adapted for high speed operation.
Attempts are continually being made to advance the state of the art in the development of faster means of conversion from an analog signal to a digital value. In a typical analog-to-digital converter, one or more comparators receive an analog signal and produce an output relative to one or more fixed analog levels. At a given sampling time the comparison result may be applied to a bistable circuit or latch for temporarily representing the level of the analog signal. The state of the latch is then read out in generating the digital result.
The most basic factor limiting high speed performance in an analog-to-digital converter circuit is the capacitance in the circuit layout and in the active devices employed. The aperture time of the circuit, during which a sample is taken, is principally affected by the time constant of the load impedance shared by the analog-to-digital comparator and subsequent circuitry. Delays in the circuit cause the sampling to be responsive to signals that existed prior to the desired sampling time. The input signal may have been changing rapidly just prior to the sampling operation and the capacitances associated with load resistors may have been charged to extreme values at a time before a sample is to be taken.
External means such as sample and hold circuits may be employed for improving the response of the system, and various kinds of switches can be utilized, but these circuits can be expensive and complex and often generate switching transients that compromise the sampling process. Such circuitry may not provide much improvement in speed.